CDx4HC125 Quadruple Buffers with 3-State Outputs

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Enable digital signals 3 Description This dev

封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUFFER NON-INVERT 6V 14DIP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

High-Speed CMOS Logic Quad Buffer, Three-State

文件：618.78 Kbytes Page：16 Pages

High Speed CMOS Logic Quad Buffer, Three-State

文件：36.72 Kbytes Page：7 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：269.45 Kbytes Page：11 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：265.02 Kbytes Page：12 Pages

CDx4HC125 Quadruple Buffers with 3-State Outputs

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Enable digital signals 3 Description This dev

CDx4HC125 Quadruple Buffers with 3-State Outputs

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Enable digital signals 3 Description This dev

High-Speed CMOS Logic Quad Buffer, Three-State

文件：618.78 Kbytes Page：16 Pages

High-Speed CMOS Logic Quad Buffer, Three-State

文件：265.02 Kbytes Page：12 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR） 描述：IC BUFFER NON-INVERT 6V 14DIP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

Quad buffer/line driver; 3-state

1. General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

QUADRUPLE 3-STATE BUFFERS OE LOW

Description The 74HC125 provides provides four independent buffer gates with 3-state outputs. Each buffer has a separate enable pin that if driven with a high logic level places the corresponding output in the high impedance state. The device is designed for operation with a power supply range of

Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien