DIGITAL PHASE-LOCKED LOOP

Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption Digital Design Avoids Analog Compensation Errors Easily Cascadable for Higher-Order Loops Useful Frequency Range – DC to 110 MHz Typical (K CLK) – DC to 70 MHz Typical (I/D CLK) Dynamically Variable Bandwidth Ve

DIGITAL PHASE-LOCKED LOOP

文件：196.72 Kbytes Page：12 Pages

DIGITAL PHASE-LOCKED LOOP

文件：463.15 Kbytes Page：18 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC DIG PHASE-LOCKED LOOP 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

DIGITAL PHASE-LOCKED LOOP

Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption Digital Design Avoids Analog Compensation Errors Easily Cascadable for Higher-Order Loops Useful Frequency Range – DC to 110 MHz Typical (K CLK) – DC to 70 MHz Typical (I/D CLK) Dynamically Variable Bandwidth Ve

DIGITAL PHASE-LOCKED LOOP

文件：196.72 Kbytes Page：12 Pages

DIGITAL PHASE-LOCKED LOOP

文件：463.15 Kbytes Page：18 Pages

DIGITAL PHASE-LOCKED LOOP

Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption Digital Design Avoids Analog Compensation Errors Easily Cascadable for Higher-Order Loops Useful Frequency Range – DC to 110 MHz Typical (K CLK) – DC to 70 MHz Typical (I/D CLK) Dynamically Variable Bandwidth Ve

DIGITAL PHASE-LOCKED LOOP

Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption Digital Design Avoids Analog Compensation Errors Easily Cascadable for Higher-Order Loops Useful Frequency Range – DC to 110 MHz Typical (K CLK) – DC to 70 MHz Typical (I/D CLK) Dynamically Variable Bandwidth Ve

DIGITAL PHASE-LOCKED LOOP

文件：463.15 Kbytes Page：18 Pages