CD74AC174 Hex D-type Flip-Flop with Clear

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Contains six flip-flops with single-rail outputs • Buffered inputs • Speed of Bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays

CD74AC174 Hex D-type Flip-Flop with Clear

1 Features • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage • Contains six flip-flops with single-rail outputs • Buffered inputs • Speed of Bipolar F, AS, and S, with significantly reduced power consumption • Balanced propagation delays

封装/外壳：16-DIP（0.300"，7.62mm） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 6BIT 16DIP 集成电路（IC） 触发器

HEX D-TYPE FLIP-FLOP

文件：833.89 Kbytes Page：14 Pages

Hex D Flip-Flop with Reset

文件：36.39 Kbytes Page：7 Pages

Hex D-Type Flip-Flop with Master Reset

General Description The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The 74AC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the clock pulse. Wh

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The 74AC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the clock pulse. Wh

HEX D-TYPE FLIP FLOP WITH CLEAR

文件：257.12 Kbytes Page：11 Pages