丝印代码：CD54HCT74F；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：CD54HCT74F；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：CD54HCT74F；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：CD54HCT74F；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

文件：276.3 Kbytes Page：12 Pages

Dual D Flip-Flop with Set and Reset

文件：628.26 Kbytes Page：17 Pages

丝印代码：5962-8685301CA；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：5962-8685301CA；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

Dual D Flip-Flop with Set and Reset

文件：628.26 Kbytes Page：17 Pages

Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

文件：276.3 Kbytes Page：12 Pages

DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

Description The M54HCxxx and M54HCTxxx series are composed of over 90 types of high speed CMOS functions specifically designed to meet the radiation requirements of the aerospace industry. It includes a large set of gates, Flip-Flops, Multiplexers, Counters, Bus interface and several other functi

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be usedas a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information a

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：533.48 Kbytes Page：15 Pages

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：533.48 Kbytes Page：15 Pages