CMOS 8-Stage Static Shift Registers

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CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：并行或串行至串行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC STATIC SHFT REG 8STG 16-SOIC 集成电路（IC） 移位寄存器

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The HCC4014B, HCC4021B (extended temperature range) and the HCF4014B, HCF4021B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. 4014B SYNCHRONOUS PARALLEL OR SERIAL INPUT/

8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The HCC4014B, HCC4021B (extended temperature range) and the HCF4014B, HCF4021B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. 4014B SYNCHRONOUS PARALLEL OR SERIAL INPUT/

8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The HCC4014B, HCC4021B (extended temperature range) and the HCF4014B, HCF4021B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. 4014B SYNCHRONOUS PARALLEL OR SERIAL INPUT/

8-bit static shift register

DESCRIPTION The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (P0 to P7) and buffered parallel outputs from th

8-bit static shift register

DESCRIPTION The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (P0 to P7) and buffered parallel outputs from th