CMOS Counter/Dividers

Features: Fully static operation = Medium-speed operation . . 10 MHz (typ) at Vpp = 10 V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V,10V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 134, “St

具有 10 个解码输出的 CMOS 十进制计数器

CMOS Counter/Dividers

文件：1.03167 Mbytes Page：19 Pages

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes Page：8 Pages

5-stage Johnson counter

DESCRIPTION The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Oo to O9), an active LOW output from the most significant flip-flop (O5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR). The