CMOS Quad D - Type Flip-Flop

Features: 100% tested for quiescent current at20v Maximum input current of 1 uA at 18 V over full package- temperature range; 100.nA at 18V and 25°C | Noise margin (full package- temperature range) = 1VatVoo=5V 2VatVop=10V 25VatVoo=15V 5-V, 10-V, and 15-V parametric ratings Meets

CMOS 四路 D 类触发器

Cd40175B consists of four identical D-type flip-flops. Each flip-flop has an independent DATA D input and complementary Q and Q\\ outputs. The CLOCK and CLEAR inputs are common to all flip-flops. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All four flip • 100% tested for quiescent current at 20 V\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD = 10 V      2.5 V at VDD = 15 V\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS ;

CMOS Quad D-type Flip-Flop

文件：940.2 Kbytes Page：18 Pages

Hex,Quad D Flip-Flop

文件：135.25 Kbytes Page：6 Pages

Hex,Quad D Flip-Flop

文件：135.25 Kbytes Page：6 Pages

Hex,Quad D Flip-Flop

文件：135.25 Kbytes Page：6 Pages

Hex,Quad D Flip-Flop

文件：135.25 Kbytes Page：6 Pages

Hex,Quad D Flip-Flop

文件：135.25 Kbytes Page：6 Pages