CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

丝印代码：CD4015BF3A；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

丝印代码：CD4015BF3A；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

丝印代码：CD4015BF3A；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

CMOS Dual 4-Stage Static Shift Register

文件：521.58 Kbytes Page：11 Pages

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages