CMOS 8 级静态移位寄存器

CD4014B and CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel \"JAM\" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In • Medium speed operation…12 MHz (typ.) clock rate at VDD – VSS = 10 V\n• 8 master-slave flip-flops plus output buffering and control gating\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Standardized, symmetrical output characteristics\n• Mee;

CMOS 8-stage Static Shift Registers

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8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The HCC4014B, HCC4021B (extended temperature range) and the HCF4014B, HCF4021B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. 4014B SYNCHRONOUS PARALLEL OR SERIAL INPUT/

8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The HCC4014B, HCC4021B (extended temperature range) and the HCF4014B, HCF4021B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. 4014B SYNCHRONOUS PARALLEL OR SERIAL INPUT/

8-bit static shift register

DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel output

8-bit static shift register

DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel output

8-bit static shift register

DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel output