Hex Buffers (Non-Inverting)

General Description The CD4010C hex buffers are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide su

CMOS 32-Stage Static Left/Right Shift Register

Description CD40100BMS is a 32-Stage shift register containing 32 D-type master-slave flip-flops. The data present at the SHIFT RIGHT INPUT is transferred into the first register stage synchronously with the positive CLOCK edge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCUL

CMOS 9-Bit Parity Generator/Checker

Description The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit) parity generator/checker. It may be used to detect errors in data transmission or data retrieval. Odd and even outputs facilitate odd or even parity generation and checking. When used as a parity generator, a parity bit is

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has c

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

CMOS 4-Bit Bidirectional Universal Shift Register

Description The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems. In the parallel load mode (S0 and S1 are high), dat

CMOS FIFO Register

Features • 4 Bits x 16 Words • High Voltage Type (20V Rating) • Independent Asynchronous Inputs and Outputs • 3-State Outputs • Expandable in Either Direction • Status Indicators on Input and Output • Reset Capability • Standardized Symmetrical Output Characteristics • 1

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

CMOS FIFO Register

Features • 4 Bits x 16 Words • High Voltage Type (20V Rating) • Independent Asynchronous Inputs and Outputs • 3-State Outputs • Expandable in Either Direction • Status Indicators on Input and Output • Reset Capability • Standardized Symmetrical Output Characteristics • 100 Tested for Quie

CMOS FIFO Register

Features • 4 Bits x 16 Words • High Voltage Type (20V Rating) • Independent Asynchronous Inputs and Outputs • 3-State Outputs • Expandable in Either Direction • Status Indicators on Input and Output • Reset Capability • Standardized Symmetrical Output Characteristics • 1

CMOS Hex Schmitt Triggers

Description CD40106BMS consists of six Schmitt trigger circuits. Each circuit functions as an inverter with Schmitt trigger action on the input. Features • High Voltage Type (20V Rating) • Schmitt Trigger Action with No External Components • Hysteresis Voltage (Typ.) - 0.9V at

CMOS Hex Schmitt Triggers

Features • High Voltage Type (20V Rating) • Schmitt Trigger Action with No External Components • Hysteresis Voltage (Typ.) - 0.9V at VDD = 5V - 2.3V at VDD = 10V - 3.5V at VDD = 15V • Noise Immunity Greater than 50% • No Limit on Input Rise and Fall Times • Low VDD to VSS Current Duri

CMOS High Voltage Logic

Features Wide supply voltage range: 3V to 15V High noise immunity: 0.70 VDD (typ.) Low power TTL compatibility: o Fan out of 2 driving 74L or 1 driving 74LS Hysteresis: o 0.40 VDD (typ.) o 0.20 VDD (guaranteed).

CMOS High Voltage Logic

Hex Schmitt Trigger Inverter in bare die form Description The CD40106B Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N-channel and P-channel enhancement transistors. The positive and negative going threshold voltages, VT+ and VT- , show lo

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CMOS High Voltage Logic

Features Wide supply voltage range: 3V to 15V High noise immunity: 0.70 VDD (typ.) Low power TTL compatibility: o Fan out of 2 driving 74L or 1 driving 74LS Hysteresis: o 0.40 VDD (typ.) o 0.20 VDD (guaranteed).

Hex Schmitt Trigger

General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors. Features ■Wide supply voltage range: 3V to 15V ■High noise immunity: 0.7 VDD(typ.) ■Low power TTL compatibili

Hex Schmitt Trigger

General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors. Features ■Wide supply voltage range: 3V to 15V ■High noise immunity: 0.7 VDD(typ.) ■Low power TTL compatibili

Hex Schmitt Trigger

General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors. Features ■Wide supply voltage range: 3V to 15V ■High noise immunity: 0.7 VDD(typ.) ■Low power TTL compatibili

Hex Schmitt Trigger

General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors. Features ■Wide supply voltage range: 3V to 15V ■High noise immunity: 0.7 VDD(typ.) ■Low power TTL compatibili

Hex Schmitt Trigger

General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors. Features ■Wide supply voltage range: 3V to 15V ■High noise immunity: 0.7 VDD(typ.) ■Low power TTL compatibili

Hex Schmitt Trigger

General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors. Features ■Wide supply voltage range: 3V to 15V ■High noise immunity: 0.7 VDD(typ.) ■Low power TTL compatibili

Hex Schmitt Trigger

General Description The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N and P-channel enhancement transistors. Features ■Wide supply voltage range: 3V to 15V ■High noise immunity: 0.7 VDD(typ.) ■Low power TTL compatibili

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER