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CD401晶体管资料

  • CD401别名:CD401三极管、CD401晶体管、CD401晶体三极管

  • CD401生产厂家:中国大陆半导体企业

  • CD401制作材料

  • CD401性质:射频/高频放大 (HF)_静噪放大 (LN)_宽频带放大

  • CD401封装形式:直插封装

  • CD401极限工作电压:25V

  • CD401最大电流允许值:0.1A

  • CD401最大工作频率:<1MHZ或未知

  • CD401引脚数:3

  • CD401最大耗散功率:0.7W

  • CD401放大倍数

  • CD401图片代号:C-67

  • CD401vtest:25

  • CD401htest:999900

  • CD401atest:0.1

  • CD401wtest:0.7

  • CD401代换 CD401用什么型号代替

CD401价格

参考价格:¥24.9415

型号:CD40101BE 品牌:Semiconductors 备注:这里有CD401多少钱,2026年最近7天走势,今日出价,今日竞价,CD401批发/采购报价,CD401行情走势销售排行榜,CD401报价。
型号 功能描述 生产厂家 企业 LOGO 操作

丝印代码:CD40102BE;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40102BE;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40102B;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40102B;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103BE;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103BE;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103BE;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103BF;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103BF;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103BF3A;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103BF3A;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103B;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40103B;CMOS 8-Stage Presettable Synchronous Down Counters

Features: . Synchronous or asynchronous preset . Medium-speed operation: fc = 3.6 MHz {typ.) @ Vpp = 10 V Cascadable 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18-V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (full pac

TI

德州仪器

丝印代码:CD40105BE;CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

TI

德州仪器

丝印代码:CD40105BE;CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

TI

德州仪器

丝印代码:CD40105BF;CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

TI

德州仪器

丝印代码:CD40105BF;CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

TI

德州仪器

丝印代码:CD40105BF3A;CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

TI

德州仪器

丝印代码:CD40105BF3A;CMOS FIFO Register

Features: # Independent asynchronous inputs and outputs ® 3state outputs ® Expandable in sither direction = Status indicators on input and output ® Reset capability ® Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 / #5.V, 10-V, and 16-V parametri

TI

德州仪器

丝印代码:CD40106BE;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BE;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BE;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BF;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BF;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BF3A;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BF3A;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106BM;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106B;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40106B;CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

TI

德州仪器

丝印代码:CD40107BE;CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

TI

德州仪器

丝印代码:CD40107BE;CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

TI

德州仪器

丝印代码:CD40107BF;CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

TI

德州仪器

丝印代码:CD40107BF;CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

TI

德州仪器

丝印代码:CD40107BF3A;CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

TI

德州仪器

丝印代码:CD40107BF3A;CMOS Dual 2-Input NAND Buffer/Driver

Features: 32 times standard B-Series output current drive sinking capability — 136 mA typ. Vpp=10V,Vps=1V 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 over full package-temperature range; 100 nA at 18 V and 25°C 5-V, 10-V, and 15-V parametric ratin

TI

德州仪器

丝印代码:CD40109BE;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109BE;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109BF;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109BF;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109BF3A;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109BF3A;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109B;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109B;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD40109B;CMOS Quad Low-to-High Voltage Level Shifter

Features: Independence of power supply sequence considerations—V cc can exceed Vp, input signals can exceed both Ve and Vpp Up and down level-shifting capability Three-state outputs with seperate enable controls Standardized, symmetrical output characteristics 100% tested for quiescent

TI

德州仪器

丝印代码:CD4010BE;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

丝印代码:CD4010BE;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

丝印代码:CD4010BF;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

丝印代码:CD4010BF;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

丝印代码:CD4010BF3A;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

丝印代码:CD4010BF3A;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

丝印代码:CD4010BM;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

丝印代码:CD4010BM;CMOS Hex Buffers/Converters

Features: = 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C 5.V, 10-V, and 15-V parametric ratings

TI

德州仪器

替换型号 功能描述 生产厂家 企业 LOGO 操作

32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER

STMICROELECTRONICS

意法半导体

CD401产品属性

  • 类型

    描述

  • Bits (#):

    8

  • Technology Family:

    CD4000

  • Supply voltage (Min) (V):

    3

  • Supply voltage (Max) (V):

    18

  • Input type:

    Standard CMOS

  • Output type:

    Push-Pull

  • Features:

    Balanced outputs

更新时间:2026-5-17 22:59:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
TI
25+
PDIP-14
21000
原装正品现货,原厂订货,可支持含税原型号开票。
TI
25+
PDIP-14
20948
样件支持,可原厂排单订货!
HARRIS
2016+
DIP
1800
只做原装,假一罚十,公司可开17%增值税发票!
HI
25+
DIP-14
3200
全新原装、诚信经营、公司现货销售!
Texas Instruments
24+25+
16500
全新原厂原装现货!受权代理!可送样可提供技术支持!
HAR
24+
DIP
1735
TOSHIBA/东芝
25+
DIP14
2178
全新原装正品支持含税
TI/德州仪器
24+
PDIP-14
9600
原装现货,优势供应,支持实单!
TI/德州仪器
23+
PDIP-14
5000
只有原装,欢迎来电咨询!
TI
16+
PDIP
10000
原装正品

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