丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

* 5-Ω Switch Connection Between Two Ports * Rail-to-Rail Switching on Data I/O Ports * Ioff Supports Partial-Power-Down Mode Operation * Flow-Through Architecture Optimizes PCB Layout * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

* 5-Ω Switch Connection Between Two Ports * Rail-to-Rail Switching on Data I/O Ports * Ioff Supports Partial-Power-Down Mode Operation * Flow-Through Architecture Optimizes PCB Layout * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

* 5-Ω Switch Connection Between Two Ports * Rail-to-Rail Switching on Data I/O Ports * Ioff Supports Partial-Power-Down Mode Operation * Flow-Through Architecture Optimizes PCB Layout * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

* 5-Ω Switch Connection Between Two Ports * Rail-to-Rail Switching on Data I/O Ports * Ioff Supports Partial-Power-Down Mode Operation * Flow-Through Architecture Optimizes PCB Layout * Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

丝印代码：CBTLV3861；LOW-VOLTAGE 10-BIT FET BUS SWITCH

5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II description/ordering information The SN74CBTLV3861 pr

Sensor-less Motor Drive IC for VTR Movie Cylinder

■ Features • Operating supply voltage range : VCC=3.0 to 5.5V, VB=4.0 to 10.5V • Reduced magnetosound using 3-phase full-wave overlap drive. Built-in power transistor. • Standby mode for minimizing power consumption • Voltage output for controlling SW power supply • Motor neutral point inpu

Direct Sequence Spread Spectrum Baseband Processor

The Intersil HFA3861 Direct Sequence Spread Spectrum (DSSS) baseband processor is part of the PRISM® 2.4GHz radio chipset, and contains all the functions necessary for a full or half duplex packet baseband transceiver. Features • Complete DSSS Baseband Processor • Processing Gain . . . . . . .

Integrated Load Switch

General Description This device is particularly suited for compact power management in portable electronic equipment where 2.5V to 8V input and 2.8A output current capability are needed. This load switch integrates a small N-Channel power MOSFET (Q1) that drives a large P-Channel power MO

Integrated Load Switch

General Description This device is particularly suited for compact power management in portable electronic equipment where 2.5V to 8V input and 2.8A output current capability are needed. This load switch integrates a small N-Channel power MOSFET (Q1) that drives a large P-Channel power MO

10-BIT FET BUS SWITCH

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