2 Hardware Features

2.1 Fuser2 MCU Core

· 32-bit Synopsys DesignWare™ ARC™ EM4 CPU

· ARCv2 16/32-bit RISC instruction set architecture

· CPU provides up to 1.6 DMIPS/MHz, 3.6 CoreMark/MHz

· Operating frequency: 20 MHz (Long Run mode) and 50 MHz (Turbo mode)

· Maximum CPU power consumption in Long Run mode: 950 μA (47.5 μA/MHz)

· Maximum CPU power consumption in Turbo mode: 2.8 mA (56 μA/MHz)

· Harvard architecture with closely coupled memories for instructions (ICCM) and data (DCCM)

· Single-precision FPU with IEEE 754 compliance

· Memory protection unit (MPU)

· 4-channel micro-DMA controller

· Timer and core watchdog

· Action-point support for debugging

· Hardware support for fast CRC32 calculation

· Programmable by customers and partners

2.2 Integrated Physical Sensors

· Low power, low noise inertial measurement unit (6DoF IMU) consisting of:

· 16-bit digital triaxial gyroscope

· 16-bit digital triaxial accelerometer

· Supports data rates up to 1600 Hz (Accelerometer), 6400 Hz (Gyroscope)

· Built in power management unit and enhanced interrupt engine (for Fuser2 wake-up)

· Auxiliary master interface:

· for direct magnetometer attachment (upgrade to 9DoF IMU)

· as OIS data interface

2.3 Integrated Low-Power Custom Core (Bosch Sensortec Core)

· Integrated low-power custom MCU (Bosch Sensortec IP)

· Optimized for simple always-on algorithms

· Internal simple interrupt engine

· Comes with integrated preprocessing algorithms from Bosch Sensortec

· Not programmable by customers

· Used in combination with Fuser2 for a more efficient power use

2.4 System Control Blocks

· Brown-out reset

· Voltage regulator for digital core

· On-chip system oscillator: 20 MHz, 50 MHz

· On-chip timer oscillator: 128 kHz

2.4.1 Reset options

Available reset sources:

· Power-on reset

· Reset pad

· Host reset command

· Core watchdog

2.4.2 Oscillators & Clocks

Available clock domains1:

· Host interface clock (up to 50 MHz in SPI mode)

· System clock (20 MHz or 50 MHz) provided by internal system oscillator

· Timer clock (64 kHz derived from 128 kHz internal timer oscillator)

· External clock (input to universal timer, from GPIO up to 1 MHz)

· JTAG debug clock (up to system clock / 8)

2.5 Host Interface

· Pin-configurable as either I2C (up to 3.4 MHz) or SPI (up to 50 MHz) slave interface

· I2C slave interface monitored by I2C watchdog

· Configurable (latched/non-latched, push-pull or open drain) host interrupt output

· Dual DMA enabled command I/O FIFO for efficient command and status handling

· Dual data FIFO sensor event batching

2.6 Memory Subsystem

2.6.1 On-Chip SRAM

256 kByte of SRAM in total, organized in nine individual RAM banks:

· 16 kByte dedicated to ICCM space

· 16 kByte dedicated to DCCM space

· 7x32 kByte RAM banks in a RAM pool, configurable to either ICCM space, DCCM space or powered off

2.6.2 ROM with Integrated Software

144 kByte of program ROM in fast-access ICCM space, containing:

· Bootloader

· BSX sensor fusion library

· Functions of standard C and math library

· OPENRTOS kernel

· SHA256 and ECDSA (NIST FIPS PUB 186-4) digital signature libraries

2.6.3 OTP

· 128 Byte OTP memory for Bosch internal factory calibration and secure boot key storage (not customer programmable)

2.7 Peripheral Subsystem

2.7.1 Secondary Master Interface 1

· Master Interface 1 (M1) configured as SPI for connection of the integrated IMU sensor, operating at 10 MHz by

default.

2.7.2 Secondary Master Interface 2

· Master Interface 2 (M2) configurable as I2C (up to 1 MHz) or SPI (up to 50 MHz) for connection of additional physical

sensors to the BHI360 (see Configuration of Master Interfaces)

· Various chip selects can be associated to M2 in SPI mode

· For more Information about the Master Interface Configuration, see Section 10.1.

2.7.3 Secondary Master Interface 3

· Master Interface 3 (M3) configurable as I2C (up to 1 MHz) for connection of additional physical sensors to the BHI360

(see Configuration of Master Interfaces)

· For more Information about the Master Interface Configuration, see Section 10.1.

2.7.4 GPIOs

· Up to 8 software configurable GPIOs available for use as CS lines, Interrupt lines or other purposes. Supported

configurations:

· Input: internal configurable pull-ups, High-Z, selectable as event interrupt source

· Output: Push/Pull, High-Z, Open Drain, selectable drive strength.

For more Information about the GPIOs configuration, see Section 10.2.

2.7.5 Universal Timers & Counter

· One 32-bit real-time counter incremented by the Timer Clock running at 64 kHz (used for time stamp generation)

· One 32-bit interval timer for generation of periodic interrupts, software counters, etc. It is driven by the timer clock

running at 64 kHz

· One 16-bit universal timer operating on an external clock input or the internal timer clock. It can trigger internal

interrupts or create external output signals, e.g. a PWM signal.

· Software API to access/program all timers & counter

2.7.6 Interrupt Sources

Various sources can generate interrupt requests to the MCU in the BHI360 (Fuser2) for which interrupt handlers can

be registered. For some interrupt sources, default handlers are already registered to ensure proper operation of the

Event-Driven Software Framework.

Interrupt requests can originate from:

· Host interface

· Host writes or read into specific host interface registers

· Host interface detects end of data transmission

· Buffer overflow or underflow during data transmission

· I2C and SPI master interfaces

· Master interface signals end of a data transmission

· GPIO events

For more detailed information about the interrupt configuration, see Section 11 Event and Interrupt Configuration.

2.7.7 Event Subsystem

· Advanced event subsystem supporting effort free time synchronization between external events and internally handled

(sensor) data

· Up to 9 event channels, which can be mapped to a variety of GPIO pins

· Any GPIO, associated to an event channel, can serve as external interrupt source

· Event triggered hardware logic for capture and storage of real-time counter value for automatic time synchronization

between external events and internal time base

For more detailed information about the interrupt configuration, see Section 11 Event and Interrupt Configuration.

2.8 Debug Interface

· 2-wire JTAG interface

· Supports direct read/write of CPU data and aux registers as well as ICCM/DCCM memory locations

· Hardware breakpoint and single step execution

· Supported with Metaware Debugger for ARC and OpenOCD for GCC