Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Description These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. All devices in this family have four receivers with a common enable control. These receivers are pin equivalent to the g

Quad Differential Drivers BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA

Description These quad differential drivers are TTL input-topseudo-ECL-differential-output used for digital data transmission over balanced transmission lines. All devices in this family have four drivers with a single enable control in a common package. Features ■ Pin-equivalent to the genera

Quad Differential Drivers BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA

Description These quad differential drivers are TTL input-topseudo-ECL-differential-output used for digital data transmission over balanced transmission lines. All devices in this family have four drivers with a single enable control in a common package. Features ■ Pin-equivalent to the genera

Quad Differential Drivers BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA

Description These quad differential drivers are TTL input-topseudo-ECL-differential-output used for digital data transmission over balanced transmission lines. All devices in this family have four drivers with a single enable control in a common package. Features ■ Pin-equivalent to the genera

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Description These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. All devices in this family have four receivers with a common enable control. These receivers are pin equivalent to the g

Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A

Description These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. All devices in this family have four receivers with a common enable control. These receivers are pin equivalent to the g