DESCRIPTION

The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33’s in a system.

FEATURES

• Green / RoHS Compliant / Lead (Pb) Free package available

• Operating Range of 3.0V to 5.5V

• 470ps Propagation Delay

• 4.0GHz Toggle Frequency

• Internal Input Pulldown Resistors

• Direct Replacement for ON Semiconductor MC10EL33, MC100EL33, and MC100LVEL33

• Transistor Count = 91 Devices

• IBIS Model Files Available on Arizona Microtek Web Site