FEATURES

Industry standard pinout and timing All Inputs, outputs and clocks are fully TTI. compatible Single +5V±10 power supply Low power, 5mW standby: 175mW active, typical • Optional PACE MODE access cycle Refresh modes: RAS-ONLY, CAS-BEFORE-RAS, and HIDDEN • 512-cycle refresh distributed across 8ms Specifications guaranteed over full military temperature range (-55°C to +125°C)

GENERAL DESCRIPTION

The AS4C1024 883C is a randomly accessed solid-state memory containing 1,048,576 bits organized in a xl-bit configuration. During READ or WRITE cycles, each bit is uniquely addressed through the 20 address bits, which are entered 10 bits (A0-A9) at a time. RAS is used to latch the first 10 bits and CAS the latter 10 bits. A READ or WRITE cycle is selected with the WE input. A logic HIGH on WE dictates READ mode while a logic LOW on WE dictates WRITE mode. During a WRITE cycle, data in (D) is latched by the falling edge of WE or CAS, whichever occurs last. If WE goes LOW prior to CAS going LOW, the output (Q) remains open (High-Z) until the next CAS cycle. If WE goes LOW after data reaches Q. Q is activated and retains the selected cell data as long as CAS remains LOW (regardless of WE or RAS). This late WE pulse results in a READ-WRITE cycle. PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row address (A0-A9) defined page boundary. The PAGE MODE cycle is always initiated with a row address strobed-in by RAS followed by a column address strobed-in by CAS. CAS may be toggled-in by holding RASLOW and strobing- in different column addresses, thus executing faster memory cycles. Returning RAS HIGH terminates the PAGE MODE operation. Returning RAS and CAS HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any RAS cycle (READ, WRITE, RAS-ONLY, CAS-BEFORE-RAS, or HID- DEN refresh) so that all 512 combinations of RAS addresses (A0-A8) are executed at least every 8ms, regardless of sequence.