General Description

The PA7536 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

Versatile Logic Array Architecture

- 12 I/Os, 14 inputs, 36 registers/latches

- Up to 36 logic cell output functions

- PLA structure with true product-term sharing

- Logic functions and registers can be I/O-buried

Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications

- Integration of multiple PLDs and random logic

- Buried counters, complex state-machines

- Comparators, decoders, multiplexers and other wide-gate functions

High-Speed Commercial and Industrial Versions

- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX)

- Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 °C temperatures

CMOS Electrically Erasable Technology

- Reprogrammable in 28-pin DIP, SOIC and PLCC packages

Flexible Logic Cell

- Up to 3 output functions per logic cell

- D,T and JK registers with special features

- Independent or global clocks, resets, presets, clock polarity and output enables

- Sum-of-products logic for output enables

Development and Programmer Support

- Anachip WinPLACE Development Software

- Fitters for ABEL and other software

- Programming support by popular third-party programmers