Design Features

Chip-first approach with Known Good Die (KGD) from probed front-end wafers

Supports all kinds of incoming wafer diameter and chip packaging media

Reconstituted wafer (chip embedding in epoxy)

Single die and multi-die solutions, possibility of embedded discrete passives

Package size: from below 1 x 1 mm² to 12 x 12 mm² (up to 25 x 25 mm² under development)

Package thickness: 0.3-1.0 mm

Single-layer RDL/dual-layer RDL

Double-sided RDL for Package-on-Package (PoP) applications under development

Several UBM types for improved reliability

BGA bump pitch down to 0.400 mm (down to 0.300 mm under development)

Bare die backside for heat spreader assembly, overmold or backside coating by tape

Standard laser marking and packing

Applications

Mobile and consumer products, baseband, RF, analog, power management

ASIC, MEMS, system solutions for medical, security, encryption, DC/DC converter, radar and automotive

Electro-Optical WLSiP, solutions for M2M communication and Internet of Things (IoT)

Extension of the technology platform to a wider field of application areas is ongoing