Description

The device consists of four independent channels of codec and digital signal processing functions on one chip. In addition to the classic A-to-D and D-to-A conversion, each channel provides termination impedance synthesis and a hybrid balance network.

Features

■ 3.3 V operation

■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance

■ Programmable µ-law, linear, or A-law modes:

— Up to 256 time slots per frame

— Supports PCM data rates of 512 kbits/s to 16.384 Mbits/s

— Double-clock mode timing compatible with ISDN standard interfaces

■ Fully programmable time-slot assignment with bit offset

■ Analog and digital loopback test modes

■ Serial microprocessor interface:

— Normal and byte-by-byte control modes

— Fast scan mode

■ Six bidirectional control leads per channel, for SLIC and line card function control

■ Differential analog output:

— Mates directly to SLICs, eliminating external components

■ Sigma-delta converters with dither noise reduction

■ Quad design to minimize package count on dense line card applications

■ Meets or exceeds ITU-T G.711—G.712 and relevant Telcordia TechnologiesTM requirements