Introduction

Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design implementation coupled with the high bandwidth of the industry-standard PCI interface. The ORCA OR3TP12 FPSC provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions.

PCI Bus Core Highlights

■ Implemented in an ORCA Series 3 base array, displacing the bottom four rows of 18 columns.

■ Core is a well-tested ASIC model.

■ Fully compliant to Revision 2.1 of PCI Local Bus Specification (and designed for Revision 2.2).

■ Operates at PCI bus speeds up to 66 MHz.

■ Comprises two independent controllers for Master and Target.

■ Meets/exceeds all requirements for PICMG *Hot Swap Friendly silicon, Full Hot Swap model, per the CompactPCI* Hot Swap Specification, PICMG 2.1 R1.0.

■ PCI SIG Hot-Plug (R1.0) compliant.

■ Four internal FIFOs individually buffer both directions of both the Master and Target interfaces:

— Both Master FIFOs are 64 bits wide by 32 bits deep.

— Both Target FIFOs are 64 bits wide by 16 bits deep.

■ Capable of no-wait-state, full-burst PCI transfers in either direction, on either the Master or Target interface. Dual 32-bit data paths extend into the FPGA logic, permitting full-bandwidth, simultaneous bidirectional data transfers of up to 264 Mbytes/s to be sustained indefinitely.

■ Can be configured to provide either two 32-bit buses (one in each direction) to be multiplexed between Master and Target, or four independent 16-bit buses.

■ Provides many hardware options in the PCI bus core that are set during FPGA logic configuration.

■ Operates within the requirements of the PCI 5 V and 3.3 V signaling environments, allowing the same device to be used in 5 V or 3.3 V PCI systems.

■ FPGA is reconfigurable via the PCI interface configuration space (as well as conventionally), allowing the FPGA to be field-updated to meet late-breaking requirements of emerging protocols.

■ Master:

— Generates all defined command codes except interrupt acknowledge and special cycle.

— Capable of acting as the systems configuration agent by booting up with the Master logic enabled.

— Provides multiple options to increase PCI bus bandwidth.

■ Target:

— Responds legally to most command codes: interrupt acknowledge, special cycle, and reserved commands ignored; memory read multiple and line handled as memory read; memory write and invalidate handled as memory write.

— Implements Target abort, disconnect, retry, and wait cycles.

— Handles delayed transactions.

— Handles fast back-to-back transactions.

— Supports programmable latency timer control.

— Method of handling wait-states is programmable to allow tailoring to different Target data access latencies.

— Decodes at medium speed.

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