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M-TDAT162G52-3BAL2中文资料
M-TDAT162G52-3BAL2数据手册规格书PDF详情
Description
The MARS2G5 P-Pro SONET/SDH interface device provides a versatile solution for quad OC-3, quad OC-12, and for single OC-48 linear datacom/telecom applications. Constructed using COM2 CMOS modular process, this device incorporates integrated SONET/SDH framing, section/line/path termination, pointer processing, and data engine blocks.
Features
■ One of the next-generation, system-on-a-chip devices of Agere Systems’ multiservice access & rate solutions MARSTM family of framers.
■ Transmission convergence and SONET/SDH terminal functionality for linear networks.
■ Versatile IC supports 155/622/2488 Mbits/s SONET/SDH interface solutions for packet over SONET (POS), packet over fiber (POF), or asynchronous transfer mode (ATM) applications.
■ Low-power 1.6 V/3.3 V operation.
SONET/SDH Interface
■ Termination of quad STS-3/STM-1, quad STS-12/STM-4, or single STS-48/STM-16.
■ Supports overhead processing for transport and path overhead bytes.
■ Optional insertion and extraction of overhead bytes via serial overhead interface.
■ STS pointer processing to align the receive frame to the system frame.
■ Support for 1 + 1 and 1:1 linear networks.
■ Full path termination and SPE extraction/insertion.
■ SONET/SDH compliant condition and alarm reporting.
■ Handles all concatenation levels of STS-3c to STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
■ Built-in diagnostic loopback modes.
■ Compliant with the following Telcordia Technologies®, ANSI®, and ITU standards:
— GR-253 CORE: SONET Transport Systems: Common Generic Criteria.
— ITU-T G.707: Network Node Interface for the Synchronous Digital Hierarchy.
— ITU-T G.803: Architecture of Transport Networks Based on the Synchronous Digital Hierarchy.
— T1.105: SONET-Basic Description including Multiplex Structure, Rates, and Formats.
— T1.105.02 SONET-Payload Mappings.
— T1.105.03 SONET-Jitter at Network Interfaces.
— T1.105.06 SONET Physical Layer Specifications.
— T1.105.07 SONET-Sub-STS-1 Interface Rates and Formats Specification.
— ITU-T I.432: B-ISDN User-Network InterfacePhysical Layer Specification.
— IETF RFC 2615: PPP over SONET/SDH.
— IETF RFC 1661: The Point-to-Point Protocol (PPP).
— IETF RFC 1662: PPP in HDLC-like Framing.
Data Processing
■ Provisionable data engine supports payload insertion/extraction for PPP, ATM, or HDLC streams.
■ Extraction and insertion of DS3 frames containing HDLC or ATM data streams for up to 16 channels.
■ Integrated UTOPIA Level 2 and Level 3 compatible physical layer interface for packets or ATM cells.
■ Provides/supports internal E3 mapping.
■ Supports DS3/PLCP and clear channel DS3 mapping.
■ Insertion and extraction of up to 16 separate data channels.
■ Direct cell/packet over fiber interface device.
■ Compliant with ATM forum, ITU standards, and IETF standards.
■ Supports generic framing procedure (GFP) protocol.
Interfaces
■ Enhanced UTOPIA interface for cell and packet transfer.
■ IEEE® 1149.1 port with BIST, scan, and boundry scan.
Microprocessor Interface
■ Up to 66 MHz synchronous.
■ 16-bit address and 16-bit data interface.
■ Synchronous or asynchronous modes available.
■ Configurable to operate with most commercial microprocessors.
M-TDAT162G52-3BAL2产品属性
- 类型
描述
- 型号
M-TDAT162G52-3BAL2
- 制造商
AGERE
- 制造商全称
AGERE
- 功能描述
MARS㈢2G5 P-Pro(TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
AGERE |
24+ |
8000 |
原装现货,特价销售 |
||||
AGERE |
23+ |
BGA/12*12 |
7000 |
绝对全新原装!100%保质量特价!请放心订购! |
|||
AGERE |
24+ |
BGA1212 |
140 |
||||
AGERE |
2022+ |
288 |
全新原装 货期两周 |
||||
AGERE |
2016+ |
BGA |
6000 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
AGERE |
23+ |
DIP-24P |
5000 |
原装正品,假一罚十 |
|||
AGERE |
25+ |
CAN3 |
18000 |
原厂直接发货进口原装 |
|||
agere |
2138+ |
BGA |
8960 |
专营BGA,QFP原装现货,假一赔十 |
|||
AGERESYSTEMS |
23+ |
BGA |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
LUCENT |
23+ |
QFP |
4 |
现货库存 |
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AGERE相关芯片制造商
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