Description

The Agere Systems Inc. FW801 device provides the analog physical layer functions needed to implement a one-port node in a cable-based IEEE 1394- 1995 and IEEE P1394a network.

Distinguishing Features

■ Compliant with IEEE P1394a Draft 2.0 Standard for a High Performance Serial Bus (Supplement)

■ Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders

■ While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port

■ Does not require external filter capacitors for PLL

■ Does not require a separate 5 V supply for 5 V link controller interoperability

■ Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies

■ Interoperable with 1394 link-layer controllers using 5 V supplies

■ Device powerdown feature to conserve energy in battery-powered applications

■ Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolation

Features

■ Provides one fully compliant cable port at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s

■ Fully supports Open HCI requirements

■ Supports arbitrated short bus reset to improve utilization of the bus

■ Supports ack-accelerated arbitration and fly-by concatenation

■ Supports connection debounce

■ Supports multispeed packet concatenation

■ Supports PHY pinging and remote PHY access packets

■ Fully supports suspend/resume

■ Supports PHY-link interface initialization and reset

■ Supports 1394a register set

■ Supports LPS/link-on as a part of PHY-link interface

■ Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus

■ Fully interoperable with FireWire† implementation of IEEE 1394-1995

■ Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V

■ Separate cable bias and driver termination voltage supply for port

Other Features

■ 48-pin TQFP package

■ Single 3.3 V supply operation

■ Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s

■ 25 MHz crystal oscillator and PLL provide transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s and link-layer controller clock at 50 MHz

■ Multiple separate package signals provided for analog and digital supplies and grounds