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DSP1627数据手册规格书PDF详情
Active Clock Frequency
The purpose of this advisory is to clarify the function of the serial I/O control registers in the DSP1620/27/28/29 devices. Specifically, it clarifies the function of the control register field that specifies the active clock frequency. The device data sheets state that the active clock frequency is a ratio of the input clock frequency on the CKI pin (DSP1627/28/29 devices) or the output clock frequency on the CKO pin (DSP1620 device). For all four devices, the actual active clock frequency is a ratio of the internal clock frequency, which can be programmed as either the input clock frequency on the CKI pin or the output of an internal clock synthesizer (PLL).
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23+ |
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BGA |
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BGA |
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AGE |
24+/25+ |
213 |
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DSP1627 芯片相关型号
- ACT-D1M32T-080F14Q
- ACT-E128K32C-120P3M
- ACT-E128K32C-300P7T
- ACT-E128K32N-150P3M
- ACT-E2M32A-150F18Q
- ACT-F2M32A-150F18Q
- ACT-F2M32C-150F18Q
- BPNGA16E-TR
- BPPGA16E-TR
- BRR1A16G-TR
- BRS2B16E
- BRT1A16G-TR
- D2525P49
- D2525P52
- D2526G41
- D2526G44
- D2526G57
- D2587P54
- D2587P56
- D2587P565
- D370-20A
- D371-22A
- D372-21BS
- D374
- D374-02A
- D571C20A
- D572-22NS
- D572C20BS
- E2505H55
- FW323
AGERE相关芯片制造商
Datasheet数据表PDF页码索引
- P1
- P2
- P3
- P4
- P5
- P6
- P7
- P8
- P9
- P10
- P11
- P12
- P13
- P14
- P15
- P16
- P17
- P18
- P19
- P20
- P21
- P22
- P23
- P24
- P25
- P26
- P27
- P28
- P29
- P30
- P31
- P32
- P33
- P34
- P35
- P36
- P37
- P38
- P39
- P40
- P41
- P42
- P43
- P44
- P45
- P46
- P47
- P48
- P49
- P50
- P51
- P52
- P53
- P54
- P55
- P56
- P57
- P58
- P59
- P60
- P61
- P62
- P63
- P64
- P65
- P66
- P67
- P68
- P69
- P70
- P71
- P72
- P73
- P74
- P75
- P76
- P77
- P78
- P79
- P80
- P81
- P82
- P83
- P84
- P85
- P86
- P87
- P88
- P89
- P90
- P91
- P92
- P93
- P94
- P95
- P96
- P97
- P98
- P99
- P100
- P101
- P102
- P103
- P104
- P105