DESCRIPTION

The ACT5230 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 32-bit system interface. The ACT5230 can issue both an integer and a floating point instruction in the same cycle.

Features

■ Full militarized QED RM5230 microprocessor

■ Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle

● 100, 133 and 150 MHz operating frequency – Consult Factory for latest speeds

● 228 Dhrystone2.1 MIPS

● SPECInt95 4.2 SPECfp95 4.5

■ System interface optomized for embedded applications

● 32-bit system interface lowers total system cost with up to 87.5 MHz operating frequency

● High performance write protocols maximize uncached write bandwidth

● Operates at processor clock divisors 2 through 8

● 5V tolerant I/Os

● IEEE 1149.1 JTAG boundary scan

■ Integrated on-chip caches

● 16KB instruction - 2 way set associative

● 16KB data - 2 way set associative

● Virtually indexed, physically tagged

● Write-back and write-through on per page basis

● Early restart on data cache misses

■ Integrated memory management unit

● Fully associative joint TLB (shared by I and D translations)

● 48 dual entries map 96 pages

● Variable page size (4KB to 16MB in 4x increments)

■ High-performance floating point unit

● Single cycle repeat rate for common single precision operations and some double precision operations

● Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations

● Single cycle repeat rate for single precision combined multiply-add operation

■ MIPS IV instruction set

● Floating point multiply-add instruction increases performance in signal processing and graphics applications

● Conditional moves to reduce branch frequency

● Index address modes (register + register)

■ Embedded application enhancements

● Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction

● I and D cache locking by set

● Optional dedicated exception vector for interrupts

■ Fully static CMOS design with power down logic

● Standby reduced power mode with WAIT instruction

● 2.5 Watts typical with less than 70 mA standby current

■ 128-pin Power Quad-4 package (F22), Consult Factory for package configuration