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UG-826中文资料

厂家型号

UG-826

文件大小

860.06Kbytes

页面数量

10

功能描述

Evaluating the HMC7044 Dual Loop Clock Jitter Cleaner

数据手册

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FEATURES Simple power connection using USB connection and on-board LDO voltage regulators

LDOs can be bypassed for power measurements

AC-coupled differential SMA connectors

SMA connectors for 2 reference Inputs 6 clock outputs

1 VCXO output Microsoft Windows®–based evaluation software with

simple graphical user interface

On-board PLL loop filter

Easy access to digital input/output and diagnostic signals

via input/output header (4 GPIOs)

Status LEDs for diagnostic signals USB computer interface

GENERAL DESCRIPTION

This user guide describe the hardware and software of the HMC7044 evaluation kit. The evaluation board schematic and printed circuit board (PCB) layout artwork can be found on the EK1HMC7044LP10B product page at www.analog.com.

The HMC7044 meets the requirements of multicarrier GSM and LTE base station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO, and to generate the low phase noise, high frequency clocks with the wider-band second PLL to drive data converter sample clock inputs.

The EV3HMC7044LP10B evaluation board is a compact, easy to use platform for evaluating all the features of the HMC7044. A 122.88 MHz VCXO is mounted on the evaluation board to provide a complete solution. All inputs and outputs are configured as differential on the evaluation board.

Full specifications on the HMC7044 are available in the product data sheet, which should be consulted in conjunction with this user guide when working with the evaluation board.

更新时间:2025-11-29 16:06:00
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