Benefits and Features

● HW Accelerator Offloads ECDSA and SHA-256

Computations from Host Processor

• FIPS 186 ECDSA P-256 Signature and Verification

• ECDH Key Exchange for Session Key

Establishment

• ECDSA-Authenticated R/W of Configurable

Memory

• FIPS 180 HMAC for Bidirectional Authentication

● SHA-256 One-Time Pad Encrypted R/W of

Configurable Memory Using an ECDH Established

Key

● One GPIO Pin with Optional Authentication Control

• Open Drain, 4mA/0.4V

• Optional SHA-256 or ECDSA-Authenticated On/Off

and State Read

• Optional ECDSA Certificate to Set On/Off after

Multiblock Hash for Secure Boot

● TRNG with NIST SP 800-90B Compliant Entropy

Source with Function to Read Out

● Optional Chip-Generated Pr/Pu Key Pairs for ECC

Operations

● 6Kb of One-Time Programmable (OTP) Memory for

User Data, Keys, and Certificates

● Unique and Unalterable, Factory-Programmed, 64-Bit

Identification Number (ROM ID)

• Optional Input Data Component to Crypto and Key

Operations

● I2C Communication up to 1MHz

● 3.3V ±10%, -40°C to +125°C Operating Range

● 10-Pin, 3mm x 3mm, Side-Wettable TDFN Package

● AEC-Q100 Grade 1

Applications

● Automotive Secure Authentication

● Identification and Calibration Automotive of Parts/

Tools/Accessories

● IoT Node Crypto-Protection

● Secure Authentication of Accessories and Peripherals

● Secure Storage of Cryptographic Keys for a Host

Controller

● Secure Boot or Download of Firmware and/or System

Parameters