GENERAL DESCRIPTION

The ADSP-21267 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Harvard Architecture. The ADSP-21267 is source code compatible with the ADSP-2136x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the ADSP-21267 is a 32-bit/40-bit floating-point processor optimized for high performance audio applications with its dualported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Code compatible with all other SHARC DSPs

The ADSP-21267 processes high performance audio while

enabling low system costs

Audio decoders and post processor-algorithms support.

Non-volatile memory can be configured to contain a

combination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2,

Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES

Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others.

See www.analog.com/SHARC for a complete list

Single-Instruction Multiple-Data (SIMD) computational

architecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating point computational

units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O —a parallel port, an SPI port, four serial

ports, a digital audio interface (DAI) and JTAG test port

DAI incorporates two precision clock generators (PCG), and

an input data port (IDP) that includes a parallel data

acquisition port (PDAP), and three programmable timers, all

under software control by the signal routing unit (SRU)

On-chip memory—1M Bit of on-chip SRAM and a dedicated

3M Bits of on-chip mask-programmable ROM

The ADSP-21267 is available with a 150 MHz core instruction

rate. For complete ordering information, see Ordering

Guide on page 43