FEATURES

► Output frequency range: 800 MHz to 12.8 GHz

► Jitter = 18 fsRMS (integration bandwidth: 100 Hz to 100 MHz)

► Jitter = 27 fsRMS (ADC SNR method)

► Wideband noise floor: −160 dBc/Hz at 12 GHz

► Retimed LVDS SYSREF output

► General-purpose pulse retimer for SYSREF, SYNC, and MCS

applications

► PLL specifications

► −239 dBc/Hz: normalized in-band phase noise floor

► −147 dBc/Hz: normalized in-band 1/f phase noise floor

► Phase detector frequency up to 500 MHz

► Reference input frequency up to 1000 MHz

► Typical spurious fPFD: −95 dBc PFD at fOUT = 12 GHz

► Reference input to output delay specifications

► Device-to-device standard deviation: 3 ps

► Temperature coefficient: 0.03 ps/°C

► Adjustment step size: < ±0.1 ps

► Multichip output phase alignment

► 3.3 V and 5 V power supplies

► Available in 48-lead, 7 mm × 7 mm LGA package

APPLICATIONS

► High performance data converter and MxFE clocking

► Wireless infrastructure (MC-GSM, 5G)

► Test and measurement

► FPGA with integrated data converters