FEATURES

400 MSPS internal DDS clock speed

48-bit frequency tuning word

14-bit programmable phase offset

Integrated 14-bit DAC

Excellent dynamic performance

Phase noise ≤ 135 dBc/Hz @ 1 KHz offset

−80 dB SFDR @ 160 MHz (±100 KHz offset IOUT)

25 Mb/s write-speed serial I/O control

200 MHz phase frequency detector inputs

655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)

Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)

8 phase/frequency profiles

1.8 V supply for device operation

3.3 V supply for I/O and charge pump

Software controlled power-down

48-lead LFCSP package

Automatic linear frequency sweeping capability (in DDS)

Programmable charge pump current (up to 4 mA)

Phase modulation capability

Multichip synchronization

Dual-mode PLL lock detect

655 MHz CML-mode PECL-compliant driver

APPLICATIONS

Agile LO frequency synthesis

FM chirp source for radar and scanning systems

Automotive radars

Test and measurement equipment

Acousto-optic device drivers