FEATURES

► Low phase noise, phase-locked loop (PLL)

► On-chip voltage controlled oscillator (VCO) tunes from 2.53

GHz to 2.95 GHz

► Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz

► 1 differential or 2 single-ended reference inputs

► Accepts CMOS, LVPECL, or LVDS references to 250 MHz

► Accepts 16.62 MHz to 33.3 MHz crystal for reference input

► Optional reference clock doubler

► Reference monitoring capability

► Revertive automatic and manual reference switchover/holdover

modes

► Glitch-free switchover between references

► Automatic recovery from holdover

► Digital or analog lock detect, selectable

► Optional zero delay operation

► Twelve 800 MHz LVDS outputs divided into 4 groups

► Each group of 3 has a 1-to-32 divider with phase delay

► Additive output jitter as low as 242 fs rms

► Channel-to-channel skew grouped outputs < 60 ps

► Each LVDS output can be configured as 2 CMOS outputs (for

fOUT ≤ 250 MHz)

► Automatic synchronization of all outputs on power-up

► Manual synchronization of outputs as needed

► SPI- and I2C-compatible serial control port

► 64-lead LFCSP

► Nonvolatile EEPROM stores configuration settings

APPLICATIONS

► Low jitter, low phase noise clock distribution

► Clock generation and translation for SONET, 10Ge, 10G FC, and

other 10 Gbps protocols

► Forward error correction (G.710)

► Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

► High performance wireless transceivers

► ATE and high performance instrumentation

► Broadband infrastructures