PRODUCT DESCRIPTION

The AD805 is a data retiming phase-locked loop designed for use with a Voltage-Controlled Crystal Oscillator (VCXO) to perform clock recovery and data retiming on Nonreturn to Zero (NRZ) data. The circuit provides clock recovery and data retiming on standard telecommunications STS-3 or STM-1 data (155.52 Mbps). A Vectron C0-434Y Series VCXO circuit is used with the AD805 for specification purposes. Similar circuit performance can be obtained using other commercially available VCXO circuits. The AD805-VCXO circuit used for clock recovery and data retiming can also be used for large factor frequency multiplication.

FEATURES

155 Mbps Clock Recovery and Data Retiming

Permits CCITT G.958 Type A Jitter Tolerance

Permits CCITT G.958 Type B Jitter Transfer

Random Jitter: 0.68 rms

Pattern Jitter: Virtually Eliminated

Jitter Peaking: Fundamentally None

Acquisition: 30 Bit Periods

Accepts NRZ Data without Preamble

Single Supply Operation: –5.2 V or +5 V

10 KH ECL Compatible