GENERAL DESCRIPTION

The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

FEATURES

11-bit, 200 MSPS output data rate per channel

Integrated noise shaping requantizer (NSR)

Performance with NSR enabled

SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS

SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS

Performance with NSR disabled

SNR: 66.5 dBFS to 70 MHz @ 185 MSPS

SFDR: 83 dBc to 70 MHz @ 185 MSPS

Low power: 0.62 W @ 185 MSPS

1.8 V analog supply operation

1.8 V LVDS (ANSI-644 levels) output

1-to-8 integer clock divider

Internal ADC voltage reference

1.75 V p-p analog input range (programmable to 2.0 V p-p)

Differential analog inputs with 800 MHz bandwidth

95 dB channel isolation/crosstalk

Serial port control

User-configurable built-in self-test (BIST) capability

Energy-saving power-down modes

APPLICATIONS

Communications

Diversity radio and smart antenna (MIMO) systems

Multimode digital receivers (3G)

WCDMA, LTE, CDMA2000

WiMAX, TD-SCDMA

I/Q demodulation systems

General-purpose software radios