GENERAL DESCRIPTION

The AD4030-24 is a 2 MSPS successive approximation register

(SAR) analog-to-digital converter (ADC) with Easy Drive™. With

a guaranteed maximum ±0.9 ppm integral nonlinearity (INL) and

no missing codes at 24-bits, the AD4030-24 achieves unparalleled

precision from −40°C to +125°C. Figure 1 shows the functional

architecture of the AD4030-24.

A low-drift, internal precision reference buffer eases voltage

reference sharing with other system circuitry. The AD4030-24 offers

a typical dynamic range of 109 dB when using a 5 V reference.

The low noise floor enables signal chains requiring less gain and

lower power. A block averaging filter with programmable decimation

ratio can increase dynamic range up to 155.5 dB. The wide

differential input and common mode ranges allow inputs to use

the full ±VREF range without saturating, simplifying signal conditioning

requirements and system calibration. The improved settling of

the Easy Drive analog inputs broadens the selection of analog

front-end components compatible with the AD4030-24. Both singleended

and differential signals are supported.

The versatile Flexi-SPI serial peripheral interface (SPI) eases host

processor and ADC integration. A wide data clocking window,

multiple SDO lanes, and optional DDR data clocking can reduce

the serial clock to 10 MHz while operating at a sample rate of 2

MSPS. Echo clock mode and ADC host clock mode relax the timing

requirements and simplify the use of digital isolators.

The BGA package of the AD4030-24 integrates all critical power

supply and reference bypass capacitors, reducing the footprint and

system component count, and lessening sensitivity to board layout.

FEATURES

► High performance

► Throughput: 2 MSPS maximum

► INL: ±0.9 ppm maximum from −40°C to +125°C

► SNR: 108.4 dB typical

► THD: −127 dB typical

► NSD: −169 dBFS/Hz typical

► Low power

► 30 mW at 2 MSPS

► 3 mW at 10 kSPS

► Easy Drive™ features reduce system complexity

► Low 1.2 μA input current for dc inputs

► Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF

► Flexible external reference voltage range: 4.096 V to 5 V

► Accurate integrated reference buffer with 2 μF bypass capacitor

► Programmable block averaging filter with up to 216 decimation

► Extended sample resolution to 30 bits

► Overrange and synchronization bits

► Flexi-SPI digital interface

► 1, 2, or 4 SDO lanes allows slower SCK

► Echo clock mode simplifies use of digital isolator

► Compatible with 1.2 V to 1.8 V logic

► 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint

APPLICATIONS

► Automatic test equipment

► Digital control loops

► Medical instrumentation

► Seismology

► Semiconductor manufacturing

► Scientific instrumentation