3.3V 2M 횞 8/1M 횞 16 CMOS synchronous DRAM

Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank sel

3.3V 2M 횞 8/1M 횞 16 CMOS synchronous DRAM

Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank sel

3.3V 2M 횞 8/1M 횞 16 CMOS synchronous DRAM

Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank sel

3.3V 2M 횞 8/1M 횞 16 CMOS synchronous DRAM

Features • Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address • All signals referenced to positive edge of clock, fully synchronous • Dual internal banks controlled by A11 (bank sel