AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-cor

单核 64 位 Arm® Cortex®-A53，单核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性

AM64x 是 Sitara™ 新增的工业级异构 Arm® 处理器产品系列，专为要求独特结合实时处理和通信与应用处理的电机驱动器和可编程逻辑控制器 (PLC) 等工业应用而构建。AM64x 将两个支持 TSN 技术的 Sitara 器件千兆位 PRU-ICSSG 实例与最多两个 Arm® Cortex®-A53 内核、最多四个 Cortex-R5F MCU 和一个 Cortex-M4F MCU 合并到一起。\n\nAM64x 旨在通过高性能 R5F 内核、紧密耦合的存储器组、可配置的 SRAM 分区和进出外设的专用低延迟路径提供出色的实时性能，从而实现数据快速进出 SoC。这种确定性架构允许 处理器内核： \n• 双核 Cortex-A53 集群（具有 256KB L2 共享缓存，包括 SECDED ECC）\n• 最多 2 个双核 Arm Cortex-R5F MCU 子系统，工作频率高达 800MHz，集成用于实现实时处理 \n• 每个 R5F 内核 32KB ICache、32KB DCache 和 64KB TCM，总共 256KB TCM，所有存储器上都有 SECDED ECC\n• 1 个单核 Arm Cortex-M4F MCU，高达 400MHz \n• 2 个千兆位工业通信子系统 (PRU_ICSSG) \n• 向后兼容 10/100Mb PRU_ICSS\n•;

AM64x Sitara Processors

文件：5.00627 Mbytes Page：237 Pages

AM64x Sitara??Processors

文件：5.77773 Mbytes Page：235 Pages

丝印代码：AM6411BKCGHAALV709；AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-cor

丝印代码：AM6411B；AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

丝印代码：AM6411B；AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

丝印代码：AM6411BSCGHAALV709；AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-cor

丝印代码：AM6411BSCGHIALV709；AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-cor

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

AM64x Sitara™ Processors

1 Features Processor cores: • 1× Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Up to 2× Dual-co

P-Channel 20-V (D-S) MOSFET

P-Channel 20-V (D-S) MOSFET These miniature surface mount MOSFETs utilize a high cell density trench process to provide low rDS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters and power management in portable and battery-powered products such a

AM64x Sitara Processors

文件：5.00627 Mbytes Page：237 Pages

AM64x Sitara??Processors

文件：5.77773 Mbytes Page：235 Pages

AM64x Sitara??Processors

文件：5.77773 Mbytes Page：235 Pages

MOSFET

Bilateral Trigger Diodes (DIACS)

Description: The NTE6407 thru NTE6412 are bilateral trigger DIACs offering a range of voltage characteristics from 28V to 63V. These devices are triggered from a blocking–to–conduction state for either polarity of applied voltage whenever the amplitude of applied voltage exceeds the breakover v

AUDIO/VIDEO SWITCH MATRIX

DESCRIPTION The STV6411A is a highly integrated I2C bus-controlled audio and video switch matrix, optimized for use in digital set-top box applications. It provides all the audio and video routings required in a full three scart set-top box design. It is also fully pin compatible with STV6410A,

AUDIO/VIDEO SWITCH MATRIX

DESCRIPTION The STV6411A is a highly integrated I2C bus-controlled audio and video switch matrix, optimized for use in digital set-top box applications. It provides all the audio and video routings required in a full three scart set-top box design. It is also fully pin compatible with STV6410A,

AUDIO/VIDEO SWITCH MATRIX

DESCRIPTION The STV6411A is a highly integrated I2C bus-controlled audio and video switch matrix, optimized for use in digital set-top box applications. It provides all the audio and video routings required in a full three scart set-top box design. It is also fully pin compatible with STV6410A,

DUAL-MODE DIGITAL CAMERA CO-PROCESSOR

DESCRIPTION STMicroelectronics Imaging Division has produced the camera co-processor STV0681 which, used with CIF/VGA sensors as part of a low cost dual-mode camera chipset, allows a new line of low cost cameras or toy products to be brought to the market. STV0681 is a mask ROM version of STV0680