AM62x Sitara™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core A

AM62x Sitara??Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core A

AM62x Sitara??Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core A

AM62x Sitara™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core A

AM62x Sitara™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core A

AM62x Sitara™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core A

AM62x Sitara™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core A

IEC1010 Compliant Test Lead Coupler

FEATURES: · Interfaces to safety style sheathed 4 mm plugs. · Provides a fast and easy method to splice two cables together to increase cable length. · Complies to IEC 1010-2-031, which is the latest international safety standard for test accessories. · For added safety, the insulation

Universal-Input/15 W 50 kHz Flyback Switching Regulators

FEATURES AND BENEFITS ■ 50 kHz PWM with ±5 Frequency Jittering Cost Reduction of EMI Noise Filtering ■ Rugged 650 V Avalanche-Rated MOSFET Simplified Surge Absorption No VDSS Derating Required ■ Choice of rDS(on) (2.8 Ω or 3.95 Ω maximum) ■ Auto-Burst Mode for Stand-By Operation or Light Lo

Universal-Input 20W 67kHz Flyback Switching Regulators

FEATURES AND BENEFITS 67 kHz PWM with ±5 frequency jittering for EMI noise filtering and cost reduction Rugged 650 V avalanche-rated MOSFET: • Simplified surge absorption • No VDSS derating required Low RDS(on) : 2.8 Ω maximum Auto-burst mode for stand-by operation or light loads; less tra