Dual, 3 V, CMOS, LVDS Differential Line Receiver

GENERAL DESCRIPTION The ADN4664 is a dual, CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device acc

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC RECEIVER 0/2 8SOIC 集成电路（IC） 驱动器，接收器，收发器

LVDS and M-LVDS Circuit Implementation Guide

INTRODUCTION Low voltage differential signaling (LVDS) is a standard for communicating at high speed in point-to-point applications. Multipoint LVDS (M-LVDS) is a similar standard for multipoint applications. Both LVDS and M-LVDS use differential signaling, a two-wire communication method where r

Dual, 3 V, CMOS, LVDS Differential Line Receiver

GENERAL DESCRIPTION The ADN4664 is a dual, CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device acc

Dual, 3 V, CMOS, LVDS Differential Line Receiver

GENERAL DESCRIPTION The ADN4664 is a dual, CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device acc

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC RECEIVER 0/2 8SOIC 集成电路（IC） 驱动器，接收器，收发器

High Q, high self-resonant frequency

Special Features • High Q, high self-resonant frequency • High voltage application • Single layer or 3-pi universal wound • Low cost • Varnish coated • Operating temperature: phenolic -55 to +125°C iron & ferrite -55 to +105°C • Current to cause 35°C maximum temperature rise

High Q, high self-resonant frequency

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Varnished Chokes

文件：108.28 Kbytes Page：1 Pages