OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

PRODUCT DESCRIPTION The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted

OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

OC-48/OC-48 FEC时钟和数据恢复

ADN2811可提供下列接收器功能：量化、信号电平检测、时钟和数据恢复，适用于OC-48和OC-48 FEC速率。该器件满足所有的SONET抖动要求，包括抖动传递、抖动产生和抖动容差。所有规格均相对于-40℃至+85癈环境温度而言，除非另有说明。\n\n 该器件主要用于WDM系统，可以结合外部参考时钟或配有外部晶振的片内振荡器使用。ADN2811同时支持2.48 Gbps和2.66 Gbps数字包装器速率，无需更改参考时钟。\n\n 该器件配合PIN二极管和TIA前置放大器，可以实现高度集成的低成本、低功耗光纤接收器。\n\n 当输入信号电平降至用户可调阈值以下时 • 符合SONET抖动传递/产生/容差要求\n\n• 量化器灵敏度：4 mV（典型值）\n\n• 可调限幅电平：±100 mV\n\n• 带宽：1.9 GHz（最小值）\n\n• 取得专利的时钟恢复架构\n\n• 信号丢失检测范围：3 mV至15 mV\n\n• 单一参考时钟频率同时适用于本有SONET和15/14 (7%)包装器速率\n\n• 选择19.44 MHz、38.88 MHz、77.76 MHz或155.52 MHz REFCLK\n\n• LVPECL/LVDS/LVCMOS/LVTTL兼容输入（LVPECL/LVDS，仅在155.52 MHz时）\n\n• 19.44 ;

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

文件：485.78 Kbytes Page：20 Pages

OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

PRODUCT DESCRIPTION The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

PRODUCT DESCRIPTION The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted

OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

OC-48/OC-48 FEC Clock and Data Recovery

FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range: 3 mV to 15 mV Single reference clock frequency for both nati

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

文件：485.78 Kbytes Page：20 Pages

封装/外壳：48-WFQFN 裸露焊盘，CSP 包装：卷带（TR） 描述：IC CLK DATA REC SDH 2.66GHZ 集成电路（IC） 应用特定时钟/定时

封装/外壳：48-WFQFN 裸露焊盘，CSP 包装：托盘 描述：IC CLK DATA REC SDH 2.66GHZ 集成电路（IC） 应用特定时钟/定时

SCHOTTKY BARRIER DIODES

FEATURES * Miniature Surface Mount Packages * Low turn-on voltage * Pico second switching speed * High breakdown voltage APPLICATIONS * Mixers * Detectors * Switching

DUAL HIGH-SPEED MOSFET DRIVERS

文件：663 Kbytes Page：31 Pages

DUAL HIGH-SPEED MOSFET DRIVERS

文件：663 Kbytes Page：31 Pages

DUAL HIGH-SPEED MOSFET DRIVERS

文件：663 Kbytes Page：31 Pages

丝印代码：E8；SCHOTTKY BARRIER DIODES

文件：104 Kbytes Page：3 Pages