Jitter Cleaner and Clock Generator

GENERAL DESCRIPTION The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. FEATURES Output frequency:

Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs

GENERAL DESCRIPTION The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. FEATURES Output frequency:

14路输出、低抖动时钟发生器

AD9523提供低功耗、多路输出时钟分配功能，具有低抖动性能，还配有片内集成锁相环(PLL)和电压控制振荡器(VCO)。片内VCO的调谐频率范围为3.6 GHz至4.0 GHz。\n\n AD9523旨在满足长期演进(LTE)和多载波GSM基站设计的时钟要求。它依靠外部VCXO清除参考抖动，以满足严格的低相位噪声要求，从而获得可接受的数据转换器信噪比(SNR)性能。\n\n 输入接收器、振荡器和零延迟接收器支持单端和差分两种操作。当连接到恢复的系统参考时钟和VCXO时，器件产生1 MHz至1 GHz范围内的14路低噪声输出，以及一路来自输入PLL (PLL1)的专用缓冲输出 • 下载示例代码\n\n• 输出频率：<1 MHz至1 GHz\n\n• 启动频率精度：<±100 ppm（由VCXO参考精度决定）\n\n• 零延迟操作\n输入至输出边沿时序：<±500 ps\n\n• 14 路输出：可配置为LVPECL、LVDS、HSTL和LVCMOS\n\n• 14 个具有零抖动可调延迟的专用输出分频器;

低抖动时钟发生器，提供14路LVPECL/LVDS/HSTL输出或29路LVCMOS输出

AD9523-1提供低功耗、多路输出时钟分配功能，具有低抖动性能，还配有片内PLL、VCO和两个VCO分频器。片内VCO的调谐频率范围为2.94 GHz至3.1 GHz。\n\n AD9523-1旨在满足长期演进(LTE)和多载波GSM基站设计的时钟要求。它依靠外部VCXO清除参考抖动，以满足严格的低相位噪声要求，从而获得可接受的数据转换器信噪比(SNR)性能。\n\n 输入接收器、振荡器和零延迟接收器支持单端和差分两种操作。当连接到恢复的系统参考时钟和VCXO时，器件产生1 MHz至1 GHz范围内的14路低噪声输出，以及一路来自输入PLL (PLL1)的专用缓冲输出。一 • 输出频率范围：<1 MHz至1 GHz\n\n• 启动频率精度：<±100 ppm（由VCXO参考精度决定）\n\n• 零延迟操作\n输入至输出边沿时序：<150 ps\n\n• 两个VCO分频器\n\n• 14 路输出：可配置为LVPECL、LVDS、HSTL和LVCMOS\n\n• 14 个具有零抖动可调延迟的专用输出分频器;

Jitter Cleaner and Clock Generator

GENERAL DESCRIPTION The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. FEATURES Output frequency:

Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs

GENERAL DESCRIPTION The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. FEATURES Output frequency:

Jitter Cleaner and Clock Generator

GENERAL DESCRIPTION The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. FEATURES Output frequency:

Low Jitter Clock Generator

文件：1.0658 Mbytes Page：63 Pages

Low Jitter Clock Generator

文件：840.33 Kbytes Page：60 Pages

功能：时钟发生器 包装：散装 描述：BOARD EVAL FOR AD9523-1 开发板，套件，编程器 评估和演示板及套件

封装/外壳：72-VFQFN 裸露焊盘，CSP 包装：管件 描述：IC INTEGER-N CLCK GEN 72LFCSP 集成电路（IC） 应用特定时钟/定时

Low Jitter Clock Generator

文件：1.0658 Mbytes Page：63 Pages

Low Jitter Clock Generator

文件：840.33 Kbytes Page：60 Pages

Low Jitter Clock Generator

文件：840.33 Kbytes Page：60 Pages

Low Jitter Clock Generator

文件：1.0658 Mbytes Page：63 Pages

Low Jitter Clock Generator

文件：840.33 Kbytes Page：60 Pages

Laser Diode Control for Fiber Optic Modules

DESCRIPTION The X9523 combines two Digitally Controlled Potentiometers (DCPs), V1 / Vcc Power-on Reset (POR) circuitry, qnd two programmable voltage monitor inputs with software and hardware indicators. All functions of the X9523 are accessed by an industry standard 2-Wire serial interface. The

P-Channel Enhancement-Mode Vertical DMOS Power FETs???

文件：73.76 Kbytes Page：2 Pages

P-Channel Enhancement-Mode Vertical DMOS Power FETs???

文件：73.76 Kbytes Page：2 Pages

Laser Diode Control for Fiber Optic Modules

文件：401.18 Kbytes Page：28 Pages