1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

GENERAL DESCRIPTION The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

封装/外壳：64-VFQFN 裸露焊盘，CSP 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 2:8 1.2GHZ 64LFCSP 集成电路（IC） 时钟缓冲器，驱动器