丝印代码：ACT573；SNx4ACT573 Octal D-Type Transparent Latches With 3-State Outputs

1 Features • Operation of 4.5V to 5.5V VCC • Inputs accept voltages to 5.5V • Maximum tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Parallel data storage • Digital bus buffer 3 Description These 8-bit latches feature 3-state outputs designed specifically for

丝印代码：ACT573；SNx4ACT573 Octal D-Type Transparent Latches With 3-State Outputs

1 Features • Operation of 4.5V to 5.5V VCC • Inputs accept voltages to 5.5V • Maximum tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Parallel data storage • Digital bus buffer 3 Description These 8-bit latches feature 3-state outputs designed specifically for

丝印代码：ACT573；SNx4ACT573 Octal D-Type Transparent Latches With 3-State Outputs

1 Features • Operation of 4.5V to 5.5V VCC • Inputs accept voltages to 5.5V • Maximum tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Parallel data storage • Digital bus buffer 3 Description These 8-bit latches feature 3-state outputs designed specifically for

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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丝印代码：ACT573M；Octal TRansparent Latch, 3-State

Family Features: Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015 SCR-Latchup-resistant CMOS process and circuit design Speed of bipolar FAST*/AS]S with significantly reduced power consumption Balanced propagation delays. AC types feature 1.5-V to 5.5-V operation and balanced noise

丝印代码：ACT573M；Octal TRansparent Latch, 3-State

Family Features: Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015 SCR-Latchup-resistant CMOS process and circuit design Speed of bipolar FAST*/AS]S with significantly reduced power consumption Balanced propagation delays. AC types feature 1.5-V to 5.5-V operation and balanced noise

丝印代码：ACT573M；Octal TRansparent Latch, 3-State

Family Features: Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015 SCR-Latchup-resistant CMOS process and circuit design Speed of bipolar FAST*/AS]S with significantly reduced power consumption Balanced propagation delays. AC types feature 1.5-V to 5.5-V operation and balanced noise

丝印代码：ACT573Q；SN74ACT573-Q1 Automotive Octal D-Type Transparent Latches With 3-State Outputs

1 Applications • Parallel data storage • Digital bus buffer 2 Description These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports,

丝印代码：ACT573Q；SN74ACT573-Q1 Automotive Octal D-Type Transparent Latches With 3-State Outputs

1 Features • Operation of 4.5V to 5.5V VCC • Inputs accept voltages to 5.5V • Maximum tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Parallel data storage • Digital bus buffer 3 Description These 8-bit latches feature 3-state outputs designed specifically for

丝印代码：ACT573Q；SN74ACT573-Q1 Automotive Octal D-Type Transparent Latches With 3-State Outputs

1 Features • Operation of 4.5V to 5.5V VCC • Inputs accept voltages to 5.5V • Maximum tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Parallel data storage • Digital bus buffer 3 Description These 8-bit latches feature 3-state outputs designed specifically for

丝印代码：ACT573Q；SN74ACT573-Q1 Automotive Octal D-Type Transparent Latches With 3-State Outputs

1 Applications • Parallel data storage • Digital bus buffer 2 Description These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports,

丝印代码：ACT573Q；SN74ACT573-Q1 Automotive Octal D-Type Transparent Latches With 3-State Outputs

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B • Available in wettable flank QFN package • Wide operating range of 1.5 V to 6 V • Inputs accept volta

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Octal D-Type Latch with 3-State Outputs With 5 V?뭈olerant Inputs

The MC74LVX573 is an advanced high speed CMOS octal latch with 3−state outputs. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. This 8−bit D−type latch is controlled by a latch enable input and an output enable input. When the output enable inpu

Schottky Barrier Rectifier

Description: The NTE573 is an axial lead metal–to–silicon power diode using the Schottky Barrier principle. State–of–the–art geometry features epitaxial construction with oxide passivation and metal overlap contact. This device is ideally suited for use in low–voltage, high–frequency inverters, a

P-CHANNEL MOS FET 5-PIN 2 CIRCUITS FOR SWITCHING

P-CHANNEL MOS FET (5-PIN 2 CIRCUITS) FOR SWITCHING The µPA573T is a super-mini-mold device provided with two MOS FET circuits. It achieves high-density mounting and saves mounting costs. FEATURES • Two source common MOS FET circuits in package the same size as SC-70 • Directly driven by ICs ha