丝印代码：ACT16373；16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhance

丝印代码：ACT16373；16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhance

丝印代码：ACT16373；16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhance

丝印代码：ACT16373；16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True Outputs Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhance

丝印代码：ACT16374；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus-Driving True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted C

丝印代码：ACT16374；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus-Driving True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted C

丝印代码：ACT16374；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus-Driving True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted C

丝印代码：ACT16374；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus-Driving True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted C

丝印代码：ACT163M；4-BIT SYNCHRONOUS BINARY COUNTERS

Inputs Are TTL-Voltage Compatible Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable description/ordering information The ’ACT163 devices are 4-bit binary counters. These synchronous, presettable counters feature an inte

丝印代码：ACT163M；4-BIT SYNCHRONOUS BINARY COUNTERS

Inputs Are TTL-Voltage Compatible Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable description/ordering information The ’ACT163 devices are 4-bit binary counters. These synchronous, presettable counters feature an inte

丝印代码：ACT163M；4-BIT SYNCHRONOUS BINARY COUNTERS

Inputs Are TTL-Voltage Compatible Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable description/ordering information The ’ACT163 devices are 4-bit binary counters. These synchronous, presettable counters feature an inte

丝印代码：ACT163M；4-BIT SYNCHRONOUS BINARY COUNTERS

Inputs Are TTL-Voltage Compatible Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable description/ordering information The ’ACT163 devices are 4-bit binary counters. These synchronous, presettable counters feature an inte

丝印代码：ACT16373QEP；16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

丝印代码：ACT16373QEP；16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

丝印代码：ACT16374QEP；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

丝印代码：ACT16374QEP；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

丝印代码：ACT16373QEP；16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

丝印代码：ACT16374QEP；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

丝印代码：ACT16373QEP；16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

丝印代码：ACT16374QEP；16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Member of the Texas Instruments Widebus Family Inpu

16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

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