丝印代码：AB841A；10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB841A；10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB841A；10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB841A；10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB841A；10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB841A；10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

丝印代码：AB841A；10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR

N-CHANNEL POWER MOSFETS

FEATURES • Lower RDS(ON) • Improved inductive ruggedness • Fast switching times • Rugged polysilicon gate cell structure • Lower input capacitance • Extended safe operation area • Improved high temperature reliability

PIN PHOTODIODE

Description Large area planar silicon photodiode mounted on a two lead PC board substrate. A clear molded lens is used to increase sensitivity. Low junction capacitance permits fast response time. Features • High photo sensitivity • Low junction capacitance • High cut-off frequency • Fast sw

PIN PHOTODIODE

Description Large area planar silicon photodiode mounted on a two lead PC board substrate. A clear molded lens is used to increase sensitivity. Low junction capacitance permits fast response time. Features • High photo sensitivity • Low junction capacitance • High cut-off frequency • Fast sw

TO-220 8A Triac

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