丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

丝印代码：AB827；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

Optocoupler, Phototransistor Output

Description In the K817P/ K827PH/ K847PH parts each channel consist of a phototransistor optically coupled to a gallium arsenide infrared-emitting diode in a 4-pin (single); 8 pin (dual); 16-pin (quad) plastic dual inline package. The elements are mounted on one leadframe providing a fixed d

High Density Mounting Type Photocoupler

PC817X Seriescontains an IRED optically coupled to a phototransistor. ( PC817A, PC817B, PC817C, PC817D ) It is packaged in a 4pin DIP, available in wide-lead spacing option and SMT gullwing lead-form option. Input-output isolation voltage(rms) is 5.0kV.Collector-emitter voltage is 80V(*) and CTR i

High Density Mounting Type Photocoupler

PC817X Seriescontains an IRED optically coupled to a phototransistor. ( PC817A, PC817B, PC817C, PC817D ) It is packaged in a 4pin DIP, available in wide-lead spacing option and SMT gullwing lead-form option. Input-output isolation voltage(rms) is 5.0kV.Collector-emitter voltage is 80V(*) and CTR i

NPN SILICON EPITAXIAL TWIN TRANSISTOR

FEATURES • High gain with low operating current |S21e|2 = 9 dB TYP. @ VCE = 2 V, IC = 7 mA, f = 2 GHz |S21e|2 = 8.5 dB TYP. @ VCE = 1 V, IC = 5 mA, f = 2 GHz • 6-pin thin-type small mini mold package • Built-in 2 transistors (2 u 2SC5179)

10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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