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A67L0618

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

A67L0618

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

文件:259.829 Kbytes Page:18 Pages

AMICC

联笙电子

A67L0618

High Speed Synchronous SRAM (ZeBL)

AMIC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL™ SRAM

General Description\nThe AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.\nThe A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM ■ Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz)\n■ Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization\n■ Signal +3.3V ± 5% power supply\n■ Individual Byte Write control capability\n■ Clock enable ( CEN) pin to enable clock and suspend operations\n■ Clock-contro;

AMIC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SR

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM

General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM

AMICC

联笙电子

High Speed Synchronous SRAM (ZeBL)

AMIC

联笙电子

1M X 18, 512K X 36 LVTTL, Flow-through ZeBL SRAM

文件:199.31 Kbytes Page:18 Pages

AMICC

联笙电子

A67L0618产品属性

  • 类型

    描述

  • Configuration:

    1M x 18

  • VCC:

    3

  • Speed:

    250

  • Temp:

    I

  • Package:

    LQFP

  • Notes:

    Pipeline

  • Available:

    EOL

更新时间:2026-8-3 11:10:00
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