8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

Low Power SRAM

8K X 8 BIT CMOS SRAM

General Description\nThe A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V.\nInputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. ■ Power Supply Range: 4.5V to 5.5V\n■ Access times: 70 ns\n   A623308A-S series:\n      Operating: 35mA (max.)\n      Standby: 10µA (max.)\n   A623308A-SI/SU series:\n      Operating: 35mA (max.)\n      Standby: 15µA (max.)\n■ Extended operating temperature range: 0°C to 70°C for -\n   S series, -25;

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

General Description The A623308A is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a voltage from 4.5V to 5.5V. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

8K X 8 BIT CMOS SRAM

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8K X 8 BIT CMOS SRAM

General Description The A623308 is a low operating current 65,536-bit static random access memory organized as 8,192 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Fe