丝印代码：9511A；TCA9511A Hot Swappable I2C Bus and SMBus Buffer

1 Features • Supports bidirectional data transfer of I2C bus signals • Operating power-supply voltage range of 2.3 V to 5.5 V • TA ambient air temperature range of -40 °C to 125 °C • 1-V Precharge on all SDA and SCL lines prevents corruption during live insertion • Accommodates standard m

丝印代码：9511A；TCA9511A Hot Swappable I2C Bus and SMBus Buffer

1 Features • Supports bidirectional data transfer of I2C bus signals • Operating power-supply voltage range of 2.3 V to 5.5 V • TA ambient air temperature range of -40 °C to 125 °C • 1-V Precharge on all SDA and SCL lines prevents corruption during live insertion • Accommodates standard m

MACHINE SCREW PAN PHILLIPS 10-32

文件：130.87 Kbytes Page：1 Pages

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this