Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

文件：430.98 Kbytes Page：23 Pages

封装/外壳：32-VFQFN 裸露焊盘 包装：托盘 描述：CLOCK SYNTHESIZE/GENERATOR/PLL 集成电路（IC） 时钟缓冲器，驱动器

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

文件：430.98 Kbytes Page：23 Pages

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

Features • Three output banks, consisting of eight LVPECL output pairs total • INx, nINx inputs can accept the following differential input levels: LVPECL, LVDS, CML • Selectable output divider values of ÷1, ÷2 and ÷4 • Maximum output frequency: 1.5GHz • Maximum input frequency: 3GHz • Bank

Low Skew, 2:1 LVPECL MUX with 1:8 Fanout and Internal Termination

文件：430.98 Kbytes Page：23 Pages

包装：托盘 描述：CLOCK SYNTHESIZE/GENERATOR/PLL 集成电路（IC） 时钟缓冲器，驱动器