1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input frequency: 250MHz • Bank skew: 30ps (maximum) • Output skew: 175ps (maximum)

1-to-10 Low Skew, LVCMOS/LVTTL Fanout Buffer

文件：211.23 Kbytes Page：14 Pages

封装/外壳：32-LQFP 包装：卷带（TR） 描述：IC CLOCK GENERATOR 32-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input frequency: 250MHz • Bank skew: 30ps (maximum) • Output skew: 175ps (maximum)

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input frequency: 250MHz • Bank skew: 30ps (maximum) • Output skew: 175ps (maximum)

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input frequency: 250MHz • Bank skew: 30ps (maximum) • Output skew: 175ps (maximum)

1-to-10 Low Skew, LVCMOS/LVTTL Fanout Buffer

文件：211.23 Kbytes Page：14 Pages

封装/外壳：32-LQFP 包装：卷带（TR） 描述：IC CLOCK GENERATOR 32-LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

时钟发生器及支持产品 10 LVCMOS OUT BUFFER/DIVIDER