4:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 4:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Four selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output fre

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：NETWORK TIMING 集成电路（IC） 时钟缓冲器，驱动器

4:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 4:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Four selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output fre

4:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 4:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Four selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output fre

Maximum output frequency

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