2:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 2:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Two selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output freq

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：NETWORK TIMING 集成电路（IC） 时钟缓冲器，驱动器

2:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 2:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Two selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output freq

2:2, Differential-to-LVPECL/LVDS Clock Multiplexer

Features • High speed 2:1 differential multiplexer with a 1:2 fanout buffer • Two differential LVPECL or LVDS output pairs • Two selectable differential PCLKx, nPCLKx input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output freq

Propagation delay

文件：668.02 Kbytes Page：23 Pages